Investigating the Influence of Process Variability on Asymmetric Multicore Processors

被引:0
作者
Goncalves, Thiago Dos Santos [1 ]
Schneider Beck, Antonio Carlos [1 ]
Lorenzon, Arthur F. [1 ]
机构
[1] Univ Fed Rio Grande do Sul UFRGS, Inst Informat, Porto Alegre, RS, Brazil
来源
2024 37TH SBC/SBMICRO/IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2024 | 2024年
关键词
Process variability; Power consumption; Performance; Asymmetric Multicore Processors; POWER MANAGEMENT;
D O I
10.1109/SBCCI62366.2024.10703977
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As transistor densities increase, power dissipation and operational temperatures rise, increasing economic and environmental costs. Asymmetric multicore processors (AMPs) have been developed to address this issue. These processors incorporate performance cores for demanding tasks and energy-efficient cores for lighter operations. They also utilize dynamic voltage and frequency scaling (DVFS) and uncore frequency scaling (UFS) to manage power consumption and temperature. However, process variations during manufacturing can lead to differences in power dissipation and maximum frequency capabilities among cores, impacting the processor's estimated lifetime and sustainable application execution. Hence, we (i) investigate the effects of process variability on the performance, power, and temperature of cores from an AMP system; (ii) study how they perform when subjected to distinct workloads and operating frequency settings; and (iii) identify optimal combinations of core mapping and operating frequencies considering process variability. Through an extensive set of experiments, we show that performance cores may have up to 5 times more power variability than efficiency cores. We also show that efficiency cores have more variability when executing memory-intensive applications, while performance cores are more susceptible to variability when executing CPU-intensive workloads.
引用
收藏
页码:110 / 114
页数:5
相关论文
共 25 条
[1]   PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems [J].
Al-hayanni, Mohammed A. Noaman ;
Rafiev, Ashur ;
Xia, Fei ;
Shafik, Rishad ;
Romanovsky, Alexander ;
Yakovlev, Alex .
IEEE TRANSACTIONS ON COMPUTERS, 2020, 69 (10) :1507-1518
[2]   Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors [J].
Carlos Saez, Juan ;
Castro, Fernando ;
Prieto-Matias, Manuel .
PROCEEDINGS OF THE 49TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, ICPP 2020, 2020,
[3]   Task Scheduling Techniques for Asymmetric Multi-Core Systems [J].
Chronaki, Kallia ;
Rico, Alejandro ;
Casas, Marc ;
Moreto, Miquel ;
Badia, Rosa M. ;
Ayguade, Eduard ;
Labarta, Jesus ;
Valero, Mateo .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2017, 28 (07) :2074-2087
[4]  
Corbetta S., 2012, ACM GREAT LAK S VLSI, P33
[5]   CoScale: Coordinating CPU and Memory System DVFS in Server Systems [J].
Deng, Qingyuan ;
Meisner, David ;
Bhattacharjee, Abhishek ;
Wenisch, Thomas F. ;
Bianchini, Ricardo .
2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), 2012, :143-154
[6]   Process Variation Aware Performance Modeling and Dynamic Power Management for Multi-Core Systems [J].
Garg, Siddharth ;
Marculescu, Diana ;
Herbert, Sebastian X. .
2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2010, :89-92
[7]  
Ghorbani M, 2012, INT SYM QUAL ELECT, P772, DOI 10.1109/ISQED.2012.6187578
[8]   MAGIC: Malicious Aging in Circuits/Cores [J].
Karim, Naghmeh ;
Kanuparthi, Arun Karthik ;
Wang, Xueyang ;
Sinanoglu, Ozgur ;
Karri, Ramesh .
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2015, 12 (01)
[9]   Cuttlefish: Library for Achieving Energy Efficiency in Multicore Parallel Programs [J].
Kumar, Sunil ;
Gupta, Akshat ;
Kumar, Vivek ;
Bhalachandra, Sridutt .
SC21: INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS, 2021,
[10]  
Lorenzon AF, 2019, SPRINGERBRIEF COMPUT, P1, DOI 10.1007/978-3-030-28719-1