NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security

被引:0
作者
Bhamidipati, Padmaja [1 ]
Vemuri, Ranga [1 ]
机构
[1] Univ Cincinnati, EECS, Cincinnati, OH 45221 USA
来源
2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 | 2024年
关键词
Network-on-Chip (NoC); Quantitative Analysis; Side-channel attacks; PROTECTED MPSOC;
D O I
10.1109/MWSCAS60917.2024.10658715
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In the realm of multi-processing systems, security challenges persist with the increasing interconnectivity of devices, especially within Network-on-Chip (NoC) architectures. Shared hardware resources between secure and malicious IPs create vulnerabilities exploited by various attacks. Side-channel attacks pose challenges due to their exploitation of implicit information leakages, relying on power consumption, electromagnetic radiation, or timing variations. In response, we introduce NoC-Armor that dynamically identifies and counters side-channel attack patterns within NoCs. NoC-Armor employs a quantitative approach, utilizing conditional probability as a metric, to examine secure and side-channel attack events. This method serves as a valuable tool for making routing decisions, ultimately enhancing the security posture of NoC architectures. Our methodology demonstrated a 50% enhancement in security resilience with minimum power and area overhead.
引用
收藏
页码:1001 / 1006
页数:6
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