Impact of Interface Trap Charges on the Performance and Reliability of Heterojunction Hetero Dielectric Vertical Non-Uniform Channel Double Gate TFET

被引：1

作者：

Macherla, Swaroop Kumar ^{[1
]}

Goel, Ekta ^{[1
]}

机构：

[1] Natl Inst Technol Warangal, Dept Elect & Commun Engn, Warangal, Telangana, India

来源：

ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY | 2025年 / 14卷 / 02期

关键词：

tunnel field effect transistor; semiconductors; heterojunction; interface trap charges; electron devices - silicon; TUNNEL FETS; MOSFET; TRANSISTOR; VOLTAGE; DESIGN; MODEL;

D O I：

10.1149/2162-8777/adaf56

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We examined the influence of interface trap charges on the performance of the source pocket heterojunction hetero dielectric vertical non-uniform channel double gate tunnel field- effect transistor (SP-HJ-HD-VNUCDG-TFET). Specifically, the effect of donor and acceptor traps on the analog/RF performance of the device was investigated. The SP-HJ-HD-VNUCDG-TFET was designed to improve the drive current of the TFET. The results of the proposed device are compared with a source pocket heterojunction vertical non-uniform channel double gate TFET (SP-HJ-VNUCDG-TFET). Several figures of merit, including cutoff frequency fT, gain bandwidth product, and the transconductance frequency product are analysed and, based on the simulation results, it appears that the SP-HJ-HD-VNUCDG-TFET is more suitable for low power switching applications compared to the SP-HJ-VNUCDG-TFET because performance of SP-HJ-HD-VNUCDG-TFET is less affected by the interface trap charges.

引用

页数：12

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