A new power-rail clamp circuit for on-chip electrostatic discharge protection

被引：0
作者：
Yue, Yaping [1 ,2 ]
Pu, Shi [3 ]
Wu, Ruizhen [2 ]
Hou, Ronghui [1 ]
机构：
[1] Xidian Univ, Sch Cyber Engn, Xian 710071, Peoples R China
[2] United Micro Technol Xian Co Ltd, Xian 710076, Peoples R China
[3] Xian Xiangteng Microelect Co Ltd, Xian 710068, Peoples R China
来源：
MICROELECTRONICS JOURNAL | 2025年 / 158卷
关键词：
Clamp voltage; Electrostatic discharge (ESD); False-triggering; Power-rail clamp circuit; ESD CLAMP; VOLTAGE; DESIGN;
D O I：
10.1016/j.mejo.2025.106617
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Power-rail clamp circuit is crucial for the whole-chip electrostatic discharge (ESD) protection. In this paper, a new power-rail clamp circuit for on-chip ESD protection is proposed and verified by silicon. A dedicated falsetriggering suppression circuit is introduced to make sure that the proposed clamp circuit keeps off during fast power-up events. By skillfully incorporating slew rate and voltage detection mechanisms are, offering a low clamp voltage and a reliable turn-off functionality. Experimental results from fabricated silicon die verify that the proposed clamp circuit exhibits high immunity to false triggering, making it suitable for robust ESD protection. Comparisons with the traditional solution are also presented.
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收藏
页数：7
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