Impedance modeling and analysis of multi-pair P/G TSVs and solder balls in 3D ICs

With the rapid development of high integration and low power consumption requirements for 3D TSV ICs, chips are stacked vertically and connected by through silicon via (TSV) to achieve inter-layer transmission. At present, the density of 3D integration technology is rising, and besides, the number of TSVs and solder balls is increasing. The electromagnetic coupling between them causes serious PI problems, so it is necessary to study the influences of TSV and solder ball size parameters on PDN impedance. In this paper, the impedance modeling and analysis of multi-pair power/ground TSVs (P/G TSVs) and solder balls in 3D integrated circuits are researched. Aiming at the structure of two-layer stacked PDN interconnected by multiple pairs of TSVs and solder balls, HFSS modeling is used to analyze the influences of changing the radius, height, oxide layer thickness, and horizontal and vertical distances of nine pairs of TSVs and solder balls on PDN impedance in 0-20 GHz frequency band. It is found that the height of the solder balls is the main factor affecting the resonant frequency. When the height of the solder balls is changed, the resonant frequency will increase. In addition, TSV radius, height, solder ball height and the vertical distance of P/G TSV pairs have significant effects on the maximum parallel resonance peak. The height of the solder balls increases from 5 mu m to 25 mu m, and the maximum parallel resonance peak value increases from 54.78 Omega to 75.8 Omega, increasing by 21.02 Omega.