Memristor-Based Reconfigurable True Time Delay Circuit

被引:0
|
作者
Yang, Fan [1 ]
Serb, Alexander [1 ]
Wang, Shiwei [1 ]
Papavassiliou, Christos [2 ]
Prodromakis, Themistoklis [1 ]
机构
[1] Univ Edinburgh, Inst Integrated Micro & Nano Syst, Ctr Elect Frontiers, Edinburgh, Scotland
[2] Imperial Coll London, Dept Elect & Elect Engn, London, England
基金
英国科研创新办公室;
关键词
analogue; CMOS; memristor; RF; RRAM; time delay; ALL-PASS FILTER; DISTRIBUTED MEMS; BANDWIDTH; RECEIVER; COMPACT; DESIGN;
D O I
10.1002/cta.4387
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A memristor-controlled CMOS reconfigurable true time delay circuit is introduced in this paper. The delay circuit includes three stages of g(m)-C all-pass filter delay elements connected in cascade and memristor-based tunable DC voltage sources. The memristor value variation changes the DC bias voltage inputs of the delay elements and thus controls the delay time indirectly: The memristor resistance changes in analogue from 10 to 17 k Omega, changing the tunable DC voltage source output from 584- to 711-mV DC voltage and the delay from 269 to 632 ps. The delay circuit can work in a frequency range from 50 MHz to 1.6 GHz with gain ripple smaller than 3 dB. The resolvable delay time step across the delay range is < 8.7 ps, troughing at as low as 0.4 ps. A delay circuit working in the MHz region is also designed to compare the performance with the GHz circuit, and a memristor-programming circuit is built to change the resistance levels of memristors.
引用
收藏
页数:13
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