3D-Aware Low Power High-level Resource Binding and Co-Design

While IC interconnect switching power contributes to overall dynamic power, reductions in interconnect power are only readily tackled during physical design, after architectural decisions have already been made. Since a chip's interconnect structure depends on the overall architecture's module connectivity, minimizing interconnect switching power requires the design flexibility that architectural decisions, such as operation binding, enable. We propose a co-design flow that integrates an interconnect-aware power optimal HLS binding methodology together with a dataflow and power aware physical placement tool to reduce overall switching power consumed not just within modules but also at the interconnects that connect them. We test our proposed co-design flow on functions extracted from MediaBench and show that, averaged over all tested benchmarks, our method reduces overall switching power by 31% and 28% for 2D and 3D IC floorplans respectively when compared to a conventional binding and timing-aware design process.