Noise Analysis of a 434-MHz Wakeup Receiver Analog Frontend Core With-93-dBm Input Sensitivity and 65-pJ/Bit Efficiency Based on a Switched Injection-Triggered Oscillator With Surface Acoustic Wave Resonator

被引：0

作者：

Meller, Georg ^{[1
]}

Gast, Florian ^{[2
]}

Protze, Florian ^{[1
]}

Wagner, Jens ^{[3
,4
]}

Ellinger, Frank ^{[3
,4
]}

Fettweis, Gerhard P. ^{[4
,5
,6
,7
]}

机构：

[1] Tech Univ Dresden, Chair Circuit Design & Network Theory CCN, D-01062 Dresden, Germany

[2] Tech Univ Dresden, Vodafone Chair Mobile Commun Syst MCS, D-01062 Dresden, Germany

[3] Tech Univ Dresden, CCN, D-01062 Dresden, Germany

[4] Tech Univ Dresden, Ctr Tactile Internet Human Inthe Loop CeTI, D-01062 Dresden, Germany

[5] Tech Univ Dresden, MCS, D-01062 Dresden, Germany

[6] Barkhausen Inst, 6G Life, D-01067 Dresden, Germany

[7] SEMECO, D-01067 Dresden, Germany

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2024年

关键词：

Oscillators; Noise; Receivers; Sensitivity; Surface acoustic waves; Resonant frequency; Filtering; Energy efficiency; Switches; Power demand; Analog frontend; noise; oscillator; surface acoustic wave (SAW) resonator; ultralow-power; wakeup receiver; SUPER-REGENERATIVE RECEIVER; LOW-POWER;

D O I：

10.1109/TMTT.2024.3482456

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The noise theory and measurement results of an ultralow-power receiver analog frontend core based on an switched injection-triggered oscillator (SITO) integrated in GlobalFoundries 22 nm fully depleted silicon on insulator (FD-SOI) technology are presented. Both an analytical time-domain description and a frequency-domain noise analysis for the SITO are derived. Using these, the influence of noise on the ramp-up behavior of the SITO is analyzed using a Monte Carlo simulation to predict the input sensitivity. The simulation runtime was reduced by a factor of 2400 compared with circuit simulations. An analog SITO receiver frontend with a Hartley oscillator powered from 0.5 V is designed and implemented. It achieves an input sensitivity of -93 dBm (measured, without coding) and a dc energy consumption per bit of 65 pJ/bit (measured), which improves the energy efficiency of state-of-theart analog receiver frontends by a factor of 4.3. The measured 3 dB input filtering bandwidth is 136 kHz. The consumed dc power scales with data rate due to bitwise duty cycling from 2 nW at 10 bps up to 3.9 mu W at 32 kbps (all measured), making it a perfect candidate for wakeup receivers. The noise model is validated by comparing the ramp-up time from measurements with the Monte Carlo simulation.

引用

页数：16