Simultaneous Optimization of Various-Sized SRAM Instances Through Machine Learning-Driven Transistor Sizing and Leafcell Circuit Pool Construction

In this paper, we present a Bayesian Optimization (BO)-based methodology for optimizing SRAM design across various configurations while meeting stringent constraints in different Process, Supply voltage, and Temperature (PVT) corners. Our method automatically extracts critical design parameters for power reduction and accelerates optimization using a BO-based approach that suggests multiple points. Additionally, our method efficiently identifies the worst PVT corners, minimizing the number of simulations by considering constraints and utilizing cubic spline interpolation to simultaneously provide optimal circuits for various size instances. By applying our approach, we achieved a significant reduction in dynamic power by 10.24% to 28.55%, access time by 1.76% to 38.16%, and cycle time by 1.20% to 27.39% across all corners while satisfying all constraints. Additionally, assuming our approach is used to optimize all size instances that can be generated by a commercial compiler, the required runtime is reduced by 96.65% to 99.87% compared to using conventional Bayesian Optimization.