A 3-segment Interpolating String DAC with Low-Cost Built-In-Self-Test Capabilities

被引:0
作者
Bruce, Isaac [1 ]
Darko, Emmanuel Nti [1 ]
Odion, Ekaniyere Oko [1 ]
Bhatheja, Kushagra [1 ]
Crabb, Matthew [1 ]
Chen, Degang [1 ]
机构
[1] Iowa State Univ, Ames, IA 50011 USA
来源
2024 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, ISVLSI | 2024年
关键词
Interpolating String DACs; Integral non-linearity (INL); BIST; ADC/DAC testing;
D O I
10.1109/ISVLSI61997.2024.00136
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a 3-segment interpolating string DAC with low-cost built-in self-test (BIST) capabilities. Through rigorous mathematical analysis, we establish explicit design constraints necessary to guarantee the linearity of the segmented DAC in the absence of device non-idealities without the use of buffer amplifiers. In addition, a BIST algorithm is proposed to estimate the INL of the proposed DAC. We validate the proposed design using simulation results of a 14-bit version of the DAC designed in TSMC 180nm technology. The BIST testing scheme is implemented in MATLAB, using a SAR ADC model. Simulation results indicate an INL estimation error of less than 0.6 LSBs for the 14-bit DAC and 14-bit ADC across 200 Monte-Carlo simulations.
引用
收藏
页码:708 / 711
页数:4
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