Fabrication of Capacitive Micromachined Ultrasonic Transducers With High-k Insulation Layer Using Silicon Fusion Bonding

被引:0
作者
Bang, Sangho [1 ]
Oh, Chaerin [1 ]
Lee, Sang-Mok [1 ]
Kim, Subeen [1 ]
Lee, Taemin [1 ]
Nam, Seunghyeon [1 ]
Jung, Joontaek [2 ]
Lee, Hyunjoo Jenny [1 ]
机构
[1] Korea Adv Inst Sci & Technol KAIST, Sch Elect Engn, Daejeon 34141, South Korea
[2] Natl Nano Fab Ctr NNFC, Div Nano Convergence Technol Dev, Daejeon 34141, South Korea
基金
新加坡国家研究基金会;
关键词
High-k dielectric materials; Insulation; Voltage; Fabrication; Silicon; Bonding; Silicon-on-insulator; Annealing; Acoustics; Ultrasonic transducers; Capacitive micromachined ultrasonic transducer (CMUT); fusion bonding; high-k material; lift-off; PROBES; CMUTS;
D O I
10.1109/JMEMS.2024.3516955
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With its excellent yield and potential for mass production, a capacitive micromachined ultrasonic transducer (CMUT) is a promising alternative solution to conventional piezoelectric ultrasound transducers. However, as CMUTs require high bias voltage for operation, reducing the voltage is a critical issue in the industry to overcome the problems of reliability and the need for high-voltage driving circuitry. One of the promising methods to reduce the high bias voltage is to increase the dielectric constant by replacing the insulation layer with a high-k material. Here, we present a new fabrication method for the high-k insulation layer CMUT that maintains the reliability and advantages of silicon wafer-bonded CMUT. Notably, our proposed process eliminates the need for additional photolithography steps to replace the insulation layer with high-k material compared to the conventional CMUT fabrication. In contrast to the conventional CMUT, which employs silicon dioxide film for insulation, our high-k CMUT exhibits a reduction in pull-in voltage of 11.3%. These results suggest the potential for enhanced sensitivity in ultrasonic imaging applications.2024-0153
引用
收藏
页码:65 / 72
页数:8
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    Fang, Sheng-Po
    Kim, Kyoung-Tae
    Schumann, Todd
    Yoon, Yong-Kyu YK
    [J]. 2017 IEEE 12TH INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS (NEMS), 2017, : 235 - 238
  • [22] Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situ method and its effective work function modulation of metal/high-k stacks
    Arimura, Hiroaki
    Oku, Yudai
    Saeki, Masayuki
    Kitano, Naomu
    Hosoi, Takuji
    Shimura, Takayoshi
    Watanabe, Heiji
    [J]. JOURNAL OF APPLIED PHYSICS, 2010, 107 (03)
  • [23] High-performance CF4 plasma treated polycrystalline silicon thin-film transistors using a high-k Tb2O3 gate dielectric
    Pan, Tung-Ming
    Li, Zhi-Hong
    [J]. APPLIED PHYSICS LETTERS, 2010, 96 (11)
  • [24] Fabrication and Compact Modeling of Low-Voltage Flexible Organic TFT Using Self-Assembly of Conductive Polymer Channel Over High-k PMMA/SrZrOx Dielectric
    Mehrolia, Mukuljeet Singh
    Kumar, Dharmendra
    Verma, Ankit
    Singh, Abhishek Kumar
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (10) : 6055 - 6060
  • [25] Metal-oxide-high-k-oxide-silicon memory structure using an Yb2O3 charge trapping layer
    Pan, Tung-Ming
    Chen, Jing-Wei
    [J]. APPLIED PHYSICS LETTERS, 2008, 93 (18)
  • [26] Memory improvement with high-k buffer layer in metal/SrBi2Nb2O/Al2O3/silicon gate stack for non-volatile memory applications
    Singh, Prashant
    Jha, Rajesh Kumar
    Singh, Rajat Kumar
    Singh, B. R.
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2018, 121 : 55 - 63
  • [27] HfO2 high-k solid-state incandescent devices: performance improvement using a Ti-embedded layer and observation of conductive paths as light-emitting sources
    Liu, Yiwei
    Yang, Can
    Zhao, Jinyan
    Wu, Shengli
    Dai, Liyan
    Niu, Gang
    [J]. NANOTECHNOLOGY, 2017, 28 (33)