DEVS FORMAL MODELING AND SIMULATION IN MANUFACTURING SYSTEMS

被引:0
|
作者
Martina, Cristina Ruiz [1 ]
Wainer, Gabriel [1 ]
机构
[1] Carleton Univ, Dept Syst & Comp Engn, Ottawa, ON, Canada
基金
加拿大自然科学与工程研究理事会;
关键词
DEVS; bottlenecks; manufacturing simulation;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Bottlenecks are a major problem for manufacturing companies because they limit the throughput of the production line. Although analytical methods have been widely studied, these methods are impractical in many cases, and simulation-based approaches, where a model of the system is developed, are needed. In this work, we show how to use DEVS as a tool to model and simulate manufacturing systems. More specifically, we propose to use it to apply the Theory of Constraints, identifying bottlenecks in the manufacturing plants and large amounts of Work in Progress.
引用
收藏
页数:13
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