A Delay-Free Decoupling Method for FPGA-Based Real-Time Simulation of Power Electronic Systems

The decoupling method based on the natural or inserted artificial delays, when applied to the simulation of power electronic (PE) systems, may encounter challenges such as inadequate length of delay lines or numerical instability and precision issues due to the high-frequency voltage/current variations at interfaces. To deal with the challenge, a delay-free decoupling method is proposed in this article. The method reduces both the dimension of matrix multiplication and the number of switch state combinations without sacrificing numerical stability and compresses the calculation progress by representing the decoupled system with the discrete state-space equation. The PE system is decoupled at the series/parallel interface of submodules, treating currents as boundary variables linked to each submodule's extended port. A preliminary formula for these variables is derived by simultaneously solving nodal voltage equations and kirchhoff voltage laws (KVL) equations. Submodule solutions are compacted and parallelized based on the discrete state-space equations. These equations are then substituted back and decomposing boundary variables into independent segments, to achieve parallelization of boundary variable solutions. The proposed method is validated through real-time simulation of cascaded PE systems on an field programmable gate array (FPGA) platform with a 250 ns time step. Results show that it achieves high precision compared to nondecoupled systems in power systems computer aided design (PSCAD) across diverse transient conditions. Additionally, it boosts the simulation scale by roughly 2-7 times on the FPGA-based platform compared to nondecoupled nodal analysis.