A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology

This paper presents a high-resolution, low jitter, and low-power 4-bit flash time-to-digital converter(TDC). As TDC is prone to PVT variation, NLMS-based calibration is used to minimize the delay variation in buffers due to PVT spreads. The proposed TDC has 5 ps resolution with a dynamic range of 20 ps. The periodic jitter is 1.78 ps. The power consumption is 1.2 mW at 25 degrees C temperature and 1.8V supply voltage. Also, this paper describes a new methodology for testing of proposed 4-bit, high-speed flash TDC and verifies the outputs using an Hspice simulator. The proposed technique is implemented with comparatively simple circuitry which consists of on-chip Phase Locked Loop (PLL), Digital-to-Time Converter (DTC), a few inverters, and Time-to-Digital converter (TDC) under test. This circuit technique avoids the use of costly sophisticated instruments which are required for the measurement of high-speed clocks. The time resolution, i.e. 5 ps is verified using input clocks at 25 MHz.