A 4ps Resolution Capacitive-Tuned Delay Pulse Shrinking Time to Digital Converter

被引：0

作者：

Tutuani, Patricia ^{[1
]}

Amankrah, Emmanuel ^{[1
]}

Geiger, Randall ^{[1
]}

机构：

[1] Iowa State Univ, Dept Elect & Comp Engn, Ames, IA 50011 USA

来源：

2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 | 2024年

关键词：

Delay line; time-to-digital converter (TDC); Vernier Delay Line; Pulse Shrinking;

D O I：

10.1109/MWSCAS60917.2024.10658890

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 12-bit Time-to-Digital Converter (TDC) that combines a pulse shrinking ring comprising an even number of inverting delay elements with a pulse-arbiter delay line. This innovative approach leverages the linearity of the pulse shrinking ring and the high-resolution capabilities of the pulse-arbiter delay line, resulting in a TDC with exceptional linearity and accuracy. With a resolution of 4ps, this TDC functions efficiently in a standard 0.18 mu m CMOS technology, offering a Full-Scale-Range (FSR) of 36600 ps.

引用

页码：1091 / 1095

页数：5

共 50 条

[1] A 6ps resolution pulse shrinking time-to-digital converter as phase detector in multi-mode transceiver
Liu, Yue
Vollenbruch, Ulrich
Chen, Yangjian
Wicpalek, Christian
Maurer, Linus
Mayer, Thomas
Boos, Zdravko
Weigel, Robert
2008 IEEE RADIO AND WIRELESS SYMPOSIUM, VOLS 1 AND 2, 2008, : 163 - +
[2] A 4-bit ultra-wideband beamformer with 4ps true time delay resolution
Roderick, JD
Krishnaswamy, H
Newton, K
Hashemi, H
CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, : 805 - 808
[3] PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION
Chen Chao
Meng Shengwei
Xia Zhenghuan
Fang Guangyou
Yin Hejun
Journal of Electronics(China), 2014, 31 (03) : 180 - 186
[4] A novel Time-To-Digital converter with 150 ps time resolution and 2.5 ns pulse-pair resolution
Andaloussi, MS
Boukadoum, M
Aboulhamid, EM
ICM 2002: 14TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2002, : 123 - 126
[5] Cascading delay line time-to-digital converter with 75 ps resolution and a reduced number of delay cells
Xie, DK
Zhang, QC
Qi, GS
Xu, DY
REVIEW OF SCIENTIFIC INSTRUMENTS, 2005, 76 (01):
[6] A BiCMOS time-to-digital converter with 30 ps resolution
Räisänen-Ruotsalainen, E
Rahkonen, T
Kostamovaara, J
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 278 - 281
[7] Implementation of a 30 ps Resolution Time to Digital Converter in FPGA
Narasimman, Raguvaran
Prabhakar, Anil
Chandrachoodan, Nitin
2015 INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN, COMPUTER NETWORKS & AUTOMATED VERIFICATION (EDCAV), 2015, : 12 - 17
[8] Two-step pulse-shrinking time-to-digital converter
Park, Young Jun
Yuan, Fei
MICROELECTRONICS JOURNAL, 2017, 60 : 45 - 54
[9] A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection utilizing Built-In Offset Pulse
Iizuka, Tetsuya
Koga, Takehisa
Nakura, Toru
Asada, Kunihiro
2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2016, : 313 - 316
[10] Monolithic time-to-digital converter with 20ps resolution
Tisa, S
Lotito, A
Giudice, A
Zappa, F
ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2003, : 465 - 468

← 1 2 3 4 5 →