A Six-Phase Harmonic-Rejection Digital Transmitter

This article presents a six-phase cell-reused digital transmitter (DTX) using 1/3 duty-cycle local oscillator (LO) signals for harmonic rejection. The 1/3 duty-cycle square wave ideally generates no 3rd-order component, thus facilitating the on-chip method to improve 3rd-order harmonic rejection (HR3). The six-phase architecture is realized with cell-reused technique and Doherty load modulation to produce higher output power and 18 efficiency peaks on the complex plane. Switch-off resistance control is implemented in the digital power amplifier (DPA) to optimize its linearity. A multi-phase injection-locking (MPIL)-based multi-phase LO generator (MPLG) is introduced for accurate and low-noise LO generation. Fabricated in 28-nm CMOS technology with a compact core size of 0.86 mm (2 ), this DTX realizes 28.3-and 27.7-dBm peak output power with 41.0% and 28.5% peak system efficiency (SE) at 0.9 and 1.7 GHz, respectively. The MPLG achieves < 1 degrees average phase error and the DTX with the 1/3 duty-cycle LOs offers more than 45-dBc HR3 over 0.7-2.5 GHz. For the LTE 20-MHz 64-QAM signal, it obtains 24.2-dBm P-avg , 27.1% average SE with - 24.8-dB error vector magnitude (EVM) at 0.89 GHz. As for the orthogonal frequency division multiplexing (OFDM) 40-MHz 256-QAM signal, the DTX obtains 22.5-dBm P-avg , 14.0% average SE with $-$ 27.6-dB EVM at 1.76 GHz.