A New Hierarchical Multi-granularity Cross-domain Addressing Approach in Datalink Networks

In this paper, we suggest a new hierarchical multi-granularity cross-domain addressing approach in datalink networks. The design of a multi-granularity cross-domain addressing mode for data link networks aims to overcome the limitations in capacity and flexibility of traditional fixed-length addressing modes.The traditional data link mainly completes the addressing between the members of a single data link, and the message cannot be exchanged between different data links, and the fixed length of addressing limits the number of data link members. This new addressing mode consists of three segments: network segment address, node segment address, and payload segment address. It effectively meets the requirements for adaptive and efficient addressing. Additionally, this addressing design takes into consideration the need for fast addressing, network capacity, and compatibility with traditional data links. An addressing protocol is specifically designed to support this new mode. To accommodate the unique characteristics of data link networks and this multi-granularity cross- domain addressing mode, segmented addressing is proposed. The improved OLSR routing protocol is utilized to handle the network segment and node segment addresses by enhancing both HELLO messages and TC messages as well as their processing methods. This ensures that it can meet the demands of a multi-granularity cross-domain addressing mode for data link networks. The MPR nodes are calculated using a greedy algorithm while the entire network routing is determined through Dijkstra's algorithm. On the other hand, internally within each node, the payload segment address assignment is completed along with distributing received data to respective payloads. The effectiveness of this proposed addressing mode has been verified using Exata software which yielded the average delay was 0.0583s and the throughput was 3842.63bits/ second. Comparing the throughput of US military LINK4A at 5000bits/second and LINKl 1 at 2250bits/second, this design achieves better performance and can better meet the needs of data link applications. These results demonstrate its capability to fulfill various requirements in data link applications.