A Pipelined ADC Calibration Technique Based on Time-Delay Neural Network with Ant Colony Optimization

被引：0

作者：

Li, Long ^{[1
]}

Yin, Yongsheng ^{[1
]}

Guo, Yuhui ^{[2
]}

Liu, Yongshun ^{[2
]}

Li, Jiashen ^{[1
]}

Deng, Honghui ^{[1
]}

Chen, Hongmei ^{[1
]}

Wu, Luotian ^{[1
]}

Li, Muqi ^{[1
]}

机构：

[1] Hefei Univ Technol, Inst VLSI Design, Hefei 230000, Peoples R China

[2] Inst Chip Technol, Chery Automot, Wuhu 241009, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2025年 / 22卷 / 06期

关键词：

pipelined ADC; calibration; time-delay neural network (TDNN); ant colony optimization (ACO); non-linearity errors; BACKGROUND CALIBRATION;

D O I：

10.1587/elex.22.20240745

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a pipelined analog-to-digital converters (ADCs) calibration method that integrates ant colony optimization (ACO) algorithm with time-delay neural network (TDNN). The proposed method uses TDNNs to calibrate the integral nonlinearity error of the ADC, and leverages the global search capability of ACO to optimize the time-delay feature dimensions and the initial parameter configuration of the neural network. This approach improves the calibration performance, reduces the model size, and avoids converging to local optima. The calibration method was evaluated using a commercial 14-bit, 1Gsps pipelined ADC chip. The results show that this method improves the SNDR from 63.80 dB to 79.31 dB, SFDR from 82.50 dB to 95.65 dB, and ENOB from 10.31 bits to 12.88 bits. Additionally, this method identifies the optimal time-delay feature combination with a 100% probability of global optimal calibration performance.

引用

页数：6

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