Design of CML-Based Odd Frequency Divider Using Delay Cell for Low-Power Application

The presented work introduces a novel approach for a low-power, area-optimized, adjustable current mode logic (CML)-based frequency divider (FD). A standalone divide-by-3 FD, divide-by-5 FD and a dual modulus 3/5 FD are proposed that are compatible with ZigBee and Bluetooth standards. These proposed architectures utilize delay cells, which reduce the number of stages and thus lower the overall power consumption of the designs. The gm over Id (gm/Id) methodology is explored for optimum design of latches, enabling efficient circuit sizing and enhanced performance. At 2.4-2.8GHz, the proposed standalone FDs consume 0.52-0.534mW and 0.487-0.49 7mW, respectively, while 3/5 FD consumes 0.565-0.570mW and 0.564-0.575mW power. These proposed designs are implemented using a TSMC 65nm CMOS process technology node, and post-layout simulated results are presented. The recent works are compared with the performances. This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).