Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers

Quantum computers are capable of performing large-scale calculations in a shorter time than conventional classical computers. Because quantum computers are realized in microscopic physical systems, unintended change in the quantum state is unavoidable due to interaction between environment, and it would lead to error in computation. Therefore, quantum error correction is needed to detect and correct errors that have occurred. In this paper, we propose quantum computer architecture for quantum error correction by taking account that the components of a quantum computer with quantum dots in silicon are divided into multiple temperature layers inside and outside the dilution refrigerator. Based on the required performance and possible processing capacity, each component was distributed in various temperature layers: the chip with qubits and the chip for generation of precise analog signals to control qubits are placed on 100 mK and 4 K stages inside the dilution refrigerator, respectively, while real-time digital processing is performed outside the dilution refrigerator. We then experimentally demonstrate the digital control sequence for quantum error correction combined with a simulator which simulates quantum states based on control commands from the digital processing system. The simulator enables the proof-of-principle experiment of system architecture independent of the development of the chips. The real time processing including determination of feed-forward operation and transmission of feed-forward operation commands is carried out by a field-programmable gate array (FPGA) outside the dilution refrigerator within 0.01 ms for bit-flip or phase-flip error corrections. This is a sufficiently short time compared to the assumed relaxation time, which is the approximate time that the quantum state can be preserved, meaning that our proposed architecture is applicable to quantum error correction.