Carrier Tunnelings on Ultrashort-Gate Junction-Less Field-Effect Transistor Designs

This study discusses tunneling problems encountered when designing ultrashort-gate junction-less field-effect transistors (FETs). Ultrathin-body silicon-on-insulator (UTB-SOI) FETs are suitable for nano-length gate designs owing to the augmented bandgap at channel regions. However, a comprehensive understanding of source-to-drain (S/D) and gate-dielectric (G/D) tunneling is essential to ensure optimal performance and reliability. In this study, numerical simulations of UTB-SOI FETs are conducted to reveal their effects. First, for S/D tunneling, only a p-channel FET (PFET) is considered critical, and larger tunneling mass eases this problem. Second, for G/D tunneling, an n-channel FET (NFET) is considered critical. Therefore, the oxide-wall UTB-SOI design is considered for the NFET, enabling a large ION/IOff$I_{\text{ON}} / I_{\text{Off}}$ and small ION/Ileak$I_{\text{ON}} / I_{\text{leak}}$ ratios for NFET and PFET. Conversely, the conventional trenched UTB-SOI is considered suitable for PFET. Moreover, the findings demonstrate that adopting hafnium oxide (HfO2$_{2}$) as the oxide material renders good FET characteristics. The optimized FET designs can facilitate the minimum gate length to be 1 nm or shorter, especially for NFETs.