A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler

被引：0

作者：

Iizuka, Yoichi ^{[1
]}

Maezono, Akihide ^{[1
]}

Saito, Wataru ^{[1
]}

Takami, Kazuhiko ^{[1
]}

Morishita, Fukashi ^{[1
]}

机构：

[1] Renesas Elect Corp, Kodaira 1878588, Japan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2025年

关键词：

Noise; Codes; Circuits; Clocks; Reflective binary codes; Frequency conversion; Delays; Voltage; Latches; Surveillance; SS-ADC; CMOS image sensor; noise reduction; high speed counter; correlated multiple sampling; SINGLE-SLOPE ADC; SHUTTER;

D O I：

10.1109/TCSI.2025.3528426

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This document presents a CMOS image sensor (CIS) with a high-speed single slope ADC(SS-ADC) that has a novel high-speed counter and can reduce temporal noise in a wide range of frequency components by enabling correlated multiple sampling (CMS) and digital correlated double sampling (DCDS) at high frame rates. The test chip was fabricated in 55nm process and has 8.3M pixels. The counter was confirmed to operate at a frequency equivalent to 5.36GHz. It uses a circuit and dedicated counter code that suppresses differential non-linearity (DNL) deterioration due to faster counter speeds. When CMS is performed 4 times at 30 frames per second (fps), the random noise is 187uVrms, which is a 31% improvement in noise compared to when CMS is not performed.

引用

页码：1105 / 1113

页数：9

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