Automated Design of a Strong-ARM Dynamic Comparator

被引：0

作者：

Jiang, Jiaquan ^{[1
,2
]}

Wu, Qingsen ^{[2
]}

Wang, Yuan ^{[3
]}

Qin, Qian ^{[3
]}

Hao, Jinglei ^{[3
]}

Chai, Chenkai ^{[3
]}

Lu, Yukai ^{[3
]}

Huang, Jiwen ^{[2
]}

Li, Lin ^{[2
]}

Ye, Zuochang ^{[3
]}

机构：

[1] Natl Innovat Platform Fus Ind & Educ Integrated C, Xiamen, Peoples R China

[2] Xiamen Univ, Sch Elect Sci & Engn, Xiamen, Peoples R China

[3] Tsinghua Univ, Sch Integrated Circuits, Beijing, Peoples R China

来源：

2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 | 2024年

关键词：

Strong-ARM comparator; dynamic comparator; gm/ID design methodology; analog design automation; HIGH-SPEED; LOW-POWER;

D O I：

10.1109/ISEDA62518.2024.10617721

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an automated design method for a Strong-ARM dynamic comparator. The dynamic characteristics of the dynamic comparator are analyzed and fitted into static characteristics, which is suitable for automatic sizing design with gm/ID method. The sizes of the transistors could be calculated by modeling the relationship with the specifications of the comparator, e.g., clock rate, power and input offset voltage. Furthermore, the automation process is implemented through an analog design tool Tsinghua Electronic Design (TED) and the design flow of the Strong-ARM dynamic comparator was verified at 40nm, 65nm and 180nm technologies respectively. Compared with the performance specifications, the maximum error of the simulation results of the input offset voltage and power consumption is approximately 3% and 6% respectively. Among them, the power consumption obtained from simulation are all lower than the performance specifications.

引用

页码：171 / 176

页数：6

共 12 条

[1] Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Babayan-Mashhadi, Samaneh
Lotfi, Reza
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (02) : 343 - 352
[2] Bandla K, 2020, IEEE REGION 10 SYMP, P52, DOI 10.1109/TENSYMP50017.2020.9230938
[3] Kickback noise reduction techniques for CMOS latched comparators
Figueiredo, Pedro M.
Vital, Joao C.
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (07) : 541 - 545
[4] Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators
He, Jun
Zhan, Sanyi
Chen, Degang
Geiger, Randall L.
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (05) : 911 - 919
[5] A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture
Raut, Gopal
Shah, Ambika Prasad
Sharma, Vishal
Rajput, Gunjan
Vishvakarma, Santosh Kumar
[J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2020, 39 (09) : 4681 - 4694
[6] The z-Transform for Analog Designers [The Analog Mind]
Razavi B.
[J]. IEEE Solid-State Circuits Magazine, 2020, 12 (03): : 8 - 14
[7] Razavi B., 2016, Design of Analog CMOS Integrated Circuits
[8] A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications
Siddharth, R. K.
Satyanarayana, Y. Jaya
Kumar, Y. B. Nithin
Vasantha, M. H.
Bonizzoni, Edoardo
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (12) : 2918 - 2922
[9] An Improved Strong Arm Comparator With Integrated Static Preamplifier
Spinogatti, Valerio
Sala, Riccardo Della
Bocciarelli, Cristian
Centurelli, Francesco
Trifiletti, Alessandro
[J]. IEEE ACCESS, 2023, 11 : 91724 - 91737
[10] A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique
Taghizadeh, Abouzar
Koozehkanani, Ziaddin Daei
Sobhi, Jafar
[J]. AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2017, 81 : 163 - 170

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