Efficient Subgraph Matching Framework for Fast Subcircuit Identification

Subcircuit identification finds wide applications in logic synthesis, physical design, and design verification. With the continuous increase in the scale of integrated circuits, the exploration of efficient identification algorithms has become a key issue. By modeling circuits as graphs, subcircuit identification can be formulated as a subgraph isomorphism problem. Previous efforts either use combinatorial methods to search for isomorphic subgraphs node-by-node, or perform learning-based methods by extracting the structural graph features using vanilla graph neural networks (GNNs). These methods either suffer from slow matching speeds or low accuracy, failing to meet the requirements of large-scale tasks. In this work, we propose a fast and accurate subgraph matching framework for large-scale circuit identification. Firstly, we propose a hypergraph representation method to capture the structure and device attributes of the circuit efficiently. Secondly, we develop an approximate matching method based on a hypergraph convolutional network (HGCN), enhanced with multiple techniques to improve the accuracy and matching speed. Finally, the potential isomorphic subgraphs identified by our HGCN method are further verified by an exact matching method. Our framework outperforms previous graph learning methods by achieving a 16.46% improvement in accuracy. Compared to exact matching methods, our identification framework demonstrates over a 20.29x speedup in matching time while maintaining high accuracy.