A Recursive Trigonometric Technique for Direct Digital Frequency Synthesizer Implementation

This paper presents a novel recursive trigonometry (RT) technique for direct digital frequency synthesizer (DDFS) implementations. Traditional DDFS systems on field programmable gate arrays (FPGAs) either require a substantial amount of read-only memory (ROM) space to store reference values or depend on intricate angle rotation functions to approximate trigonometric values. The proposed RT technique offers a DDFS architecture without using the lookup table (LUT) method, and it can enhance signal accuracy and minimize power consumption. The effectiveness of the proposed RT technique has been implemented in a 13.5 kHz 16-bit DDFS with a minimum of 18.91 mW and was tested on a Lattice FPGA. The effectiveness of the proposed RT technology is assessed by using different FPGA platforms in terms of accuracy, hardware resource efficiency, and power consumption, especially in generating cosine waveforms.