CMOS Schottky Diode Impedance Modeling for Varying Input Power to achieve a High ηRF-DC Rectifier Design over a Wide Input Power Range

This paper presents the design of a highly efficient single-stage voltage doubler rectifier circuit in the 180 nm CMOS process for wireless power transfer applications. An impedance modeling of the CMOS Schottky diode has been proposed in this work, where the model performs an extensive analysis of the rectifier input impedance for varying range of input power and frequency. The model considers all possible combinations of number of fingers (NF) and width by length (W/L) ratio of the Schottky diode model to determine the optimum diode sizing combination that yields the closest possible 50 Omega and minimum (0 Omega) reactance matching. An on-chip series inductor is integrated with the rectifier as part of the matching network to balance the capacitive effect from the diode and minimize the reactance variation. Measured power conversion efficiency (PCE) performance of the rectifier incorporating the optimum NF and W/L diode sizing shows that it can achieve > 60% PCE for 6-14 dBm input power range and a peak PCE of 72%. On the contrary, the rectifier incorporating the matching network can achieve a measured > 60% PCE over a wide input power range of 2 - 14 dBm and a higher peak PCE of 81.5%.