A High Critical Charge 16T Soft-Error-Aware SRAM for Aerospace Applications

Transistors are being scaled aggressively to improve the speed of operation and achieve a higher integrated density. This tendency decreases the critical charge at sensitive nodes. Consequently, SRAM cells deployed in the high radiation environment of aerospace are highly susceptible to soft errors. This paper proposes an inside-aware-soft-error 16T (IASE16T) SRAM cell for aerospace applications to address single-event upsets (SEUs). It outperforms other soft error-aware SRAM cells (SARP12T, LWS14T, SAR14T, RSP14T, S8P8N16T, EDP12T, SIS10T) by fully recovering from SEUs, superior stability, and write latency time. Simulation results indicate that IASE16T demonstrates significantly improved critical charge (exceeding 105fc) and hold stability (approximately 60%-138%). All these improvements have been achieved at a slightly higher power consumption, moderate read access time, and minor area penalty.