Hierarchical Optimization based on Partial Performance Tradeoff Modeling Method for Large Scale Analog Circuits

被引:0
|
作者
Yu, Xinyu [1 ]
机构
[1] Fudan Univ, Sch Microelect, Shanghai, Peoples R China
来源
2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 | 2024年
基金
中国国家自然科学基金;
关键词
analog circuit; partial Pareto Front; hierarchical optimization; DESIGN;
D O I
10.1109/ISEDA62518.2024.10617836
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a partial performance tradeoff modeling method is proposed for the hierarchical optimization of large analog systems. The key idea is to extract partial Pareto front model around the optimized block-level target performances instead of extracting the complete one. An iterative method based on Bayesian optimization is further proposed to update the partial model and, simultaneously, optimize the entire system. Our experimental results demonstrate that compared to the state-of-the-art methods, our proposed method can achieve a 3.0. cost reduction without surrendering any performances.
引用
收藏
页码:149 / 154
页数:6
相关论文
共 50 条
  • [1] Hierarchical modeling and simulation of large analog circuits
    Tan, SXD
    Qi, ZY
    Li, H
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 740 - 741
  • [2] Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits
    Tao, Jun
    Liao, Changhai
    Zeng, Xuan
    Li, Xin
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (01) : 23 - 36
  • [3] Hierarchical Neural Networks Method for Fault Diagnosis of Large-Scale Analog Circuits
    College of Electric and Information Engineering, Hunan University, Changsha, 410082, China
    Tsinghua Science and Technology, 2007, 12 (SUPPL. 1): : 260 - 265
  • [4] Performance space modeling for hierarchical synthesis of analog integrated circuits
    Gielen, G
    McConaghy, T
    Eeckelaert, T
    42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005, 2005, : 881 - 886
  • [5] Large-Scale Statistical Performance Modeling of Analog and Mixed-Signal Circuits
    Li, Xin
    Zhang, Wangyang
    Wang, Fa
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [6] Hierarchical symbolic analysis of large analog circuits with totally coded method
    Xu, Jing-Bo
    Journal of Donghua University (English Edition), 2006, 23 (02) : 59 - 62
  • [7] Optimization based on surrogate modeling for analog integrated circuits
    Yengui, Firas
    Labrak, Lioua
    Russo, Patrice
    Frantz, Felipe
    Abouchi, Nacer
    2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012, : 9 - 12
  • [8] Hierarchical fault modeling for linear analog circuits
    Nagi, N
    Abraham, JA
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1996, 10 (1-2) : 89 - 99
  • [9] Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors
    Liao, Changhai
    Tao, Jun
    Yu, Handi
    Tang, Zhangwen
    Su, Yangfeng
    Zhou, Dian
    Zeng, Xuan
    Li, Xin
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (12) : 2148 - 2152
  • [10] Efficient symbolic analysis method for large-scale analog circuits
    Iordache, M
    Dumitriu, L
    Mandache, L
    SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2003, : 353 - 356