Low-iteration hybrid computing CORDIC architecture

CORDIC (Coordinate Rotational Digital Computer) algorithm is widely used due to its simplicity and flexibility. The main drawbacks of CORDIC are its high number of iterations and the introduction of errors by scale factorization. To address these problems, this paper proposes a new hybrid CORDIC algorithm architecture which can effectively reduce the hardware complexity and decrease the number of iterations for faster computation by selecting rotation mode. After experimental comparisons, the number of iterations is reduced by about 3 times compared with the original research. This study verifies the feasibility of the proposed CORDIC algorithm architecture by calculating sine and cosine functions. The error between the calculated value and the true value is approximately 0.00004. This design uses 180-nm CMOS technology and operates at 1V, with an overall power consumption of 374 pJ. Compared to the current advanced CORDIC algorithm, the power consumption has been reduced by 1.5 %. Delay decreased by 12.8 %.