CDE: A Novel CGRA Development Environment with Fast Design Space Exploration Framework

被引：0

作者：

Chen, Sichao ^{[1
]}

Dai, Yuan ^{[1
]}

Zhang, Jide ^{[1
]}

Kuang, Huizhen ^{[1
]}

Gao, Xuchen ^{[1
]}

Luk, Wai-Shing ^{[1
]}

Yin, Wenbo ^{[1
]}

Wang, Lingli ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab Integrated Chips & Syst, Shanghai, Peoples R China

来源：

2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 | 2024年

基金：

中国国家自然科学基金;

关键词：

CGRA; design space exploration; graph analysis; agile hardware design;

D O I：

10.1109/ISEDA62518.2024.10618029

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Coarse-grained reconfigurable array (CGRA) hardware design optimization is hampered by time-consuming design exploration and evaluation methods. This paper proposes CDE, a novel CGRA Development Environment with a graph-analysis-based fast design space exploration (DSE) framework and an accurate hardware evaluation tool. CDE significantly improves the efficiency of CGRA architecture development, paving the way for agile hardware design.

引用

页码：772 / 772

页数：1

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