Efficient Design of a Hyperdimensional Processing Unit for Multi-Layer Cognition

被引:0
|
作者
Ibrahim, Mohamed [1 ]
Kim, Youbin [1 ]
Rabaey, Jan M. [1 ]
机构
[1] Univ Calif Berkeley, Berkeley Wireless Res Ctr, EECS Dept, Berkeley, CA 94704 USA
来源
2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE | 2024年
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中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The methodology used to design and optimize the very first general-purpose hyperdimensional (HD) processing unit capable of executing a broad spectrum of HD workloads (called "HPU") is presented. HD computing is a brain-inspired computational paradigm that uses the principles of high-dimensional mathematics to perform cognitive tasks. While considerable efforts have been spent toward realizing efficient HD processors, all of these targeted specific application domains, most often pattern classification. In contrast, the HPU design addresses the multiple layers of a cognitive process. A structured methodology identifies the kernel HD computations recurring at each of these layers, and maps them onto a unified and parameterized architectural model. The effectiveness in terms of runtime and energy consumption of the approach is evaluated. The results show that the resulting HPU efficiently processes the full range of HD algorithms, and far outperforms baseline implementations on a GPU.
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页数:6
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