Nonlinearity Analysis of Down-Sampled Paths in High-Speed ADC-Based SerDes Receivers

被引：0
|
作者：
Joshi, Archit [1 ]
机构：
[1] Intel Corp, Bengaluru 560103, India
来源：
IEEE ACCESS | 2025年 / 13卷
关键词：
Receivers; Decision feedback equalizers; Multiplexing; Histograms; Bandwidth; Voltage; Probability density function; Linearity; Gain; Feeds; Nonlinearity; down-sampling; variable gain amplifier; continuous time linear equalizer; decision feedback equalization; feed forward equalization;
D O I：
10.1109/ACCESS.2025.3545668
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Analog-to-Digital Converter (ADC) based Serializer- Deserializer (SerDes) receivers perform down-sampling in analog domain to address the speed limitation of the ADCs. This paper presents an analysis of the impact of down-sampling on nonlinearity of the analog data path. The nonlinearity is derived to quantify the contribution of down-sampled and non-down-sampled paths. The effect of bandwidth of down-sampled path on nonlinearity is analyzed. Nonlinearity estimators are proposed to distinguish between down-sampled and non-down-sampled path nonlinearity in real time receiver operation. The proposed analysis is applied to a 50 Gbps ADC based receiver.
引用
收藏
页码：38698 / 38703
页数：6
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