HNMC: Hybrid Near-Memory Computing Circuit for Neural Network Acceleration

The state-of-the-art lookup table (LUT)-based solution usually requires large-size memory which hampers the implementation of a high speed and small area computing scheme. To minimize the area while achieving a fast speed, this brief presents a hybrid near-memory computing (HNMC) circuit with a new LUT reduction technique to accelerate the LUT-based multiplication in neural network. Experimental results show that compared to the 4-bit multipliers based on pure LUT, pure logic and near-memory computing (NMC) circuits, the multiplier based on HNMC reduces up to 75% delay, 81% area and 80% power consumption; the 8-bit convolution engine based on HNMC increases throughput by 2x and reduces area up to 77% and power consumption up to 40% compared to the state-of-the-art NMC convolution engine.