A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS

被引：0

作者：

Gangasani, G. ^{[1
]}

Mostafa, A. ^{[1
]}

Singh, A. ^{[1
]}

Storaska, D. ^{[1
]}

Prabakaran, D. ^{[1
]}

Mohammad, K. ^{[1
]}

Baecher, M. ^{[1
]}

Shannon, M. ^{[1
]}

Sorna, M. ^{[1
]}

Wielgos, M. ^{[1
]}

Jenkins, P. ^{[1
]}

Ramakrishna, P. ^{[1
]}

Shukla, U. ^{[1
]}

机构：

[1] Marvell Semicond Inc, AMS, Dept Cent Engn, Santa Clara, CA 95054 USA

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2025年 / 8卷

关键词：

Transceivers; Clocks; Phase measurement; Chiplets; Transmitters; Table lookup; Solid state circuits; Phase locked loops; Electrostatic discharges; Codes; Extremely short reach (XSR); fractionally spaced ISI; PAM-4; SST; trans-admittance trans-impedance (TAS-TIS); transceiver;

D O I：

10.1109/LSSC.2025.3526877

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This letter uses 113-Gb/s PAM4 transceiver in 5-nm CMOS to demonstrate a 1.8-Tb/s chiplet, over die-to-die extremely short-reach (XSR) intrapackage links, in an 8-port configuration. The 16-channels range from 1 to 12 dB of loss at F-baud/2. The chiplet performance over these channels is better than BER < 10(-9), while consuming <1.1-pJ/b power and 0.22-mm(2) area per lane. The performance targets are achieved using an transceiver equalization strategy which minimizes 0.5-UI ISI by design in the data path and using a LUT-based TX FFE-3 for signal equalization and envelope adaptation.

引用

页码：33 / 36

页数：4