Al2O3 growth on Ge by low-temperature (∼90 °C) atomic layer deposition and its application for MOS devices

被引：0
作者：
Aso, Taisei [1 ]
Kuwazuru, Hajime [1 ]
Wang, Dong [2 ]
Yamamoto, Keisuke [2 ,3 ]
机构：
[1] Kyushu Univ, Interdisciplinary Grad Sch Engn Sci, 6-1 Kasuga Koen, Kasuga, Fukuoka 8158580, Japan
[2] Kyushu Univ, Fac Engn Sci, 6-1 Kasuga Koen, Kasuga, Fukuoka 8158580, Japan
[3] Kumamoto Univ, Res & Educ Inst Semicond & Informat, 2-39-1 Kurokami,Chuo Ku, Kumamoto 8608555, Japan
来源：
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING | 2025年 / 190卷
关键词：
Ge; Gate stack; Atomic layer deposition; Low-temperature process; ALD; TRIS(DIMETHYLAMINO)SILANE; SILICON; IMPACT; FILMS; SIO2;
D O I：
10.1016/j.mssp.2025.109372
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-temperature device process is necessary for germanium (Ge) and germanium tin (GeSn)-based novel electronics/optics/spintronics/flexible device applications. Concerning insulating layer formation for gate stack and passivation layer, atomic layer deposition (ALD) has been widely studied and applied due to advantages, as exemplified by precise film thickness control and excellent step coverage. However, low-temperature ALD has not been applied to the abovementioned Ge(Sn)-based novel devices. In this study, we investigated Al2O3 deposition using low-temperature (similar to 90 degrees C) ALD (without sample heating) on Ge substrates and examined methods to enhance film quality and electrical properties. We found that direct low-temperature ALD on Ge led to dimple formation, which we attribute to uneven ALD growth caused by variations in surface hydrophilicity. To avoid this, we introduced a GeO2 underlayer formed by electron cyclotron resonance (ECR) plasma before lowtemperature ALD, successfully preventing dimples and improving surface uniformity. The resulting Al/Al2O3/GeO2/Ge metal-oxide-semiconductor (MOS) capacitor demonstrated enhanced electrical characteristics. Additionally, a MOS field-effect transistor (FET) with gate stacks fabricated at a maximum gate stack process temperature of 130 degrees C exhibited typical operational behavior. This low-temperature ALD approach offers a promising pathway for low-temperature gate stack and passivation layer fabrication in emerging Ge(Sn)-based device applications.
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页数：6
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