Analytical multistage thermal resistance model for NSFET self-heating effects

As semiconductor technology nodes continue to scale down to 3 nm, the self-heating effect in Gate-All-Around Nanosheet Field-Effect Transistors (GAA-NSFETs) has become a significant concern. This issue arises due to the complex interaction between device dimensions, material properties, and thermal management, which can lead to performance degradation and reliability challenges in advanced transistor designs. This paper aims to investigate the self-heating phenomenon in three-stacked nanosheet FETs and to develop a novel thermal resistance model that accurately captures the thermal behavior of these devices. The goal is to create a reliable framework for analyzing and mitigating self-heating effects in nanosheet-based transistors. We employed TCAD and SPICE simulations to analyze the self-heating effect in nanosheet FETs. A new multi-stage thermal resistance model (TRM), incorporating both thermal resistance (Rth) and thermal capacitance (Cth), was developed within the Berkeley Short-channel IGFET Model-Common MultiGate (BSIM-CMG) framework. Model accuracy was ensured by fitting the simulated ID-VG curves to experimental data, followed by parameter extraction and calibration based on self-heating evaluations. The proposed multi-stage Rth model demonstrated strong agreement with the simulation results, providing an accurate representation of the thermal behavior in three-stacked nanosheet FETs. This model offers a robust tool for analyzing self-heating effects in advanced nanosheet devices and can be used to guide the design and optimization of future low-power, high-performance transistors.