Research on High-Efficiency Asynchronous Superscalar Processors

With the rapid popularization of mobile devices and smart hardware, copuled with the growing trend towards intelligence, the application of processor has been extended to nearly all fields of information technology. These fields now demand more stringent requirements in terms of processor performance and power. Traditional superscalar processors, which utilize a global clock control design, face limitations in enhancing pipeline depth and superscalar width as circuit sizes and transistor densities increase. This constraint impedes the potential performance enhancements of the processors. At the same time the clock circuit itself is not involved in data operations, it contributes to significant dynamic power consumption issues. Therefore, this paper proposes a novel asynchronous superscalar fine-grained processing method that utilizes local fine-grained, multi-level asynchronous micropipelines for overall control. This enhances both the superscalar width and pipeline depth. Based on this method, an asynchronous superscalar processor architecture is implemented, featuring an on-demand operational mechanism where start-stop transitions do not require reinitialization, enabling improved performance while reducing dynamic power.