Configurable Multi-Layer Perceptron-Based Soft Sensors on Embedded Field Programmable Gate Arrays: Targeting Diverse Deployment Goals in Fluid Flow Estimation

被引:0
作者
Ling, Tianheng [1 ]
Qian, Chao [1 ]
Klann, Theodor Mario [1 ]
Hoever, Julian [1 ]
Einhaus, Lukas [1 ]
Schiele, Gregor [1 ]
机构
[1] Univ Duisburg Essen, Intelligent Embedded Syst Comp Sci, D-47057 Duisburg, Germany
关键词
Internet of Things; embedded systems; fluid flow estimation; soft sensors; quantized neural networks; quantization-aware training; hardware-software co-design; embedded FPGA-based acceleration; energy efficiency;
D O I
10.3390/s25010083
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
This study presents a comprehensive workflow for developing and deploying Multi-Layer Perceptron (MLP)-based soft sensors on embedded FPGAs, addressing diverse deployment objectives. The proposed workflow extends our prior research by introducing greater model adaptability. It supports various configurations-spanning layer counts, neuron counts, and quantization bitwidths-to accommodate the constraints and capabilities of different FPGA platforms. The workflow incorporates a custom-developed, open-source toolchain ElasticAI.Creator that facilitates quantization-aware training, integer-only inference, automated accelerator generation using VHDL templates, and synthesis alongside performance estimation. A case study on fluid flow estimation was conducted on two FPGA platforms: the AMD Spartan-7 XC7S15 and the Lattice iCE40UP5K. For precision-focused and latency-sensitive deployments, a six-layer, 60-neuron MLP accelerator quantized to 8 bits on the XC7S15 achieved an MSE of 56.56, an MAPE of 1.61%, and an inference latency of 23.87 mu s. Moreover, for low-power and energy-constrained deployments, a five-layer, 30-neuron MLP accelerator quantized to 8 bits on the iCE40UP5K achieved an inference latency of 83.37 mu s, a power consumption of 2.06 mW, and an energy consumption of just 0.172 mu J per inference. These results confirm the workflow's ability to identify optimal FPGA accelerators tailored to specific deployment requirements, achieving a balanced trade-off between precision, inference latency, and energy efficiency.
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页数:28
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