High-performance Sparsity-aware NPU with Reconfigurable Comparator-multiplier Architecture

-Sparsity-aware neural processing units have been studied to exploit computational skipping on less important features in the neural network models. However, neural network layers typically show various matrix densities, so the hardware performance varies depending on the layer characteristics. In this paper, we introduce a reconfigurable comparator-multiplier architecture, so we can dynamically change the number of comparator/multiplier modules. The proposed reconfigurable architecture increases the throughput by 1.06-17.00x compared to the previous sparsity- aware hardware accelerators.