Automated Matching Placement Generation in Analog Circuits

被引：0

作者：

Chen, Yanning ^{[1
]}

Zhao, Dongyan ^{[1
]}

Liu, Fang ^{[1
]}

Zhao, Yang ^{[1
]}

Fu, Zhen ^{[1
]}

Shao, Yali ^{[1
]}

Zhang, Dong ^{[1
]}

Pan, Yucheng ^{[2
]}

Meng, Xiangyu ^{[2
]}

机构：

[1] Beijing Smart Chip Microelect Technol Co Ltd, State Grid Key Lab Power Ind Chip Reliabil Technol, Beijing, Peoples R China

[2] Sun Yat Sen Univ, Sch Elect & Informat Technol, Guangzhou, Peoples R China

来源：

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2025年 / 25卷 / 01期

关键词：

Analog circuit; matching device; optimization; placement; EDA; MOSFETs;

D O I：

10.5573/JSTS.2025.25.1.71

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The layout of matching devices is crucial in analog circuit design as it impacts matching, parasitic effects, and performance. Common-centroid layout, a popular method, minimizes mismatches but designing an efficient algorithm is challenging. This paper introduces a comprehensive automated matching placement algorithm for analog circuits, optimizing both common-centroid requirements and device positions to enhance accuracy and minimize area. Under the premise of minimizing performance degradation, we implemented a fully automated process from netlist to final design, demonstrating effective matching placement for transistor arrays in differential pairs and current mirrors, significantly reducing layout area and parasitic effects.

引用

页码：71 / 81

页数：11

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