Automated design methodology for IC sizing in wide tuning range multi-mode VCOs

被引：0

作者：

Qu, Zhan ^{[1
]}

Chen, Zhenjiao ^{[2
,3
]}

Shi, Xingqiang ^{[3
]}

Zhao, Ya ^{[1
]}

Zhang, Guohe ^{[1
]}

Liang, Feng ^{[1
]}

机构：

[1] Xi An Jiao Tong Univ, Sch Microelect, Xian 710049, Peoples R China

[2] Northwestern Polytech Univ, Sch Elect & Informat, Xian, Peoples R China

[3] China Elect Technol Grp Corp, Res Inst 58, Wuxi, Peoples R China

来源：

IET POWER ELECTRONICS | 2025年 / 18卷 / 01期

基金：

中国国家自然科学基金;

关键词：

circuit optimization; CMOS integrated circuits; genetic algorithms; Pareto optimisation; voltage-controlled oscillators; BAYESIAN OPTIMIZATION;

D O I：

10.1049/pel2.12842

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To address the great labour challenge arising from sizing a wide tuning range (TR) multi-mode voltage-controlled oscillator (VCO) manually, an electronic design automation methodology is proposed in this paper, which can optimize multiple circuit dimensions and design objectives of the wide TR multi-mode VCO simultaneously, achieving outstanding performance. NSGA-II algorithm substantially is extended and customized with many wide TR multi-mode VCO design considerations to develop the VCO centred variant, i.e. FNSGA-II algorithm. Using the 55 nm CMOS process, optimizations were performed on various topologies (dual-mode, triple-mode, and quad-mode) of wide TR multi-mode VCOs, demonstrating the algorithm's versatility and efficiency. Then, among many non-dominated solutions, a rule-based selection method to choose robust and practical solutions is proposed. Compared to other IC optimization algorithms, the proposed algorithm significantly enhances convergence efficiency and the diversity of superior solutions.

引用

页数：8