Fault-Tolerant Self-Timed Counters

被引：0

作者：

A. A. Zatsarinny ^{[1
]}

Yu. A. Stepchenkov ^{[1
]}

Yu. G. Diachenko ^{[1
]}

D. V. Khilko ^{[1
]}

G. A. Orlov ^{[1
]}

D. Yu. Diachenko ^{[1
]}

机构：

[1] Institute of Informatics Problems, Federal Research Center “Computer Science and Control” of Russian Academy of Sciences, Moscow

来源：

Russian Microelectronics | 2024年 / 53卷 / 8期

基金：

俄罗斯科学基金会;

关键词：

bi-phase signal; binary counter; DICE; fault tolerance; indication; Quatro; self-timed circuits; soft error;

D O I：

10.1134/S1063739724700999

中图分类号：

学科分类号：

摘要：

Abstract: The article studies the fault-tolerant self-timed (ST) counter design problem. Combinational ST circuits have a higher fault tolerance in comparison with synchronous counterparts due to redundant information coding and mandatory acknowledgment of all initiated circuit cells’ switch completion. Sequential ST circuits, including counters, are more sensitive to soft errors because a soft error can change a state stored by their memory cells. For their fault-tolerant implementation, special circuitry methods, namely DICE and Quatro, are used. They are similar to the data processing channel duplication, but use transistor cross-connection in the circuit cells. This approach significantly reduces the likelihood of a change in the counter bit’s state due to a soft error. The article proposes DICE-type and Quatro-type ST counter cases, compares their features, and resumes recommendations for the fault-tolerant ST counter implementation. © Pleiades Publishing, Ltd. 2024.

引用

页码：798 / 802

页数：4

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