Performance-aware routing optimization for graphene nanoribbon interconnects

被引:0
作者
Das, Subrata [1 ]
Deb, Arighna [2 ]
Das, Debesh Kumar [3 ]
Pandit, Soumya [1 ]
机构
[1] Univ Calcutta, Inst Radio Phys & Elect, Kolkata, India
[2] Kalinga Inst Ind Technol, Sch Elect Engn, Bhubaneswar, Orissa, India
[3] Jadavpur Univ, Dept Comp Sci & Engn, Kolkata, India
来源
SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES | 2025年 / 50卷 / 01期
关键词
Crosstalk; graphene nanoribbon interconnect; routing; interconnect resistance; interconnect delay;
D O I
10.1007/s12046-024-02666-x
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The use of graphene nanoribbon (GNR) interconnects has received significant attention in the domain of VLSI interconnects. Unlike conventional VLSI interconnects, routing GNR interconnects poses unique challenges due to their limited bending capabilities, restricted to angles of 0 degrees\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$0<^>{\circ }$$\end{document}, 60 degrees\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$60<^>{\circ }$$\end{document}, and 120 degrees\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$120<^>{\circ }$$\end{document}. The hybrid cost of GNR interconnects, which includes resistance, depends on both the length of the interconnect and the bending angles it undergoes. This paper presents the development of a routing tree for circuits utilizing GNR interconnects, with a primary objective of minimizing the product of crosstalk effects, total resistance, and interconnect delay. Our algorithm is subjected to thorough testing using a random dataset, resulting in highly promising outcomes.
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页数:12
相关论文
共 28 条
[21]  
Samanta T., Khatun S., Rahaman H., Dasgupta P., Crosstalk aware coupled line delay tree construction for on-chip interconnects, 2011 12th International Symposium on Quality Electronic Design, pp. 1-6, (2011)
[22]  
Xue T., Kuh S.E., Wang D., Post global routing crosstalk risk estimation and reduction, in Proceedings of International Conference on Computer Aided Design, pp. 302-309, (1996)
[23]  
Alpert J.C., Devgan A., Quay T.S., Buffer insertion for noise and delay optimization, Proceedings of the 35th annual Design Automation Conference, pp. 362-367, (1998)
[24]  
Zhao Wen S., Yin Wen Y., Signal integrity analysis of graphene nano-ribbon (gnr) interconnects, in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 227-230, (2012)
[25]  
Sahoo M., Rahaman H., An abcd parameter based modeling and analysis of crosstalk induced effects in multilayer graphene nano ribbon interconnects, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1138-1142, (2014)
[26]  
Sahoo M., Rahaman H., Analysis of crosstalk-induced effects in multilayer graphene nanoribbon interconnects, J. Circuits Syst. Comput, 26, (2017)
[27]  
Zhou H., Wong D.F., Global routing with crosstalk constraints, IEEE Trans. Comput. Aided Des. Int. Circuits Syst, 18, pp. 1683-1688, (1999)
[28]  
Sakura T., Tamaru K., Simple formulas for two-and three-dimensional capacitance, IEEE Trans. Electron Devices, 30, pp. 183-185, (1983)