Features of TCAD and SPICE Simulation of a Charged Particle Impact into a 6T SRAM Cell Manufactured Using the CMOS 28-nm Technology Node

被引：0

作者：

Petrosyants, K.O. ^{[1
,2
]}

Silkin, D.S. ^{[1
]}

Popov, D.A. ^{[1
]}

Ismail-Zade, M.R. ^{[1
]}

Kharitonov, I.A. ^{[1
]}

Pereverzev, L.E. ^{[3
]}

Morozov, A.A. ^{[3
]}

Turgenev, P.V. ^{[3
]}

机构：

[1] National Research University Higher School of Economics, Moscow

[2] Institute for Design Problems in Microelectronics, Russian Academy of Sciences, Moscow

[3] ООО AlphaCHIP, Moscow

来源：

Russian Microelectronics | 2024年 / 53卷 / 07期

关键词：

memory cell; particle impact; SPICE simulation; SRAM; static memory; TCAD simulation;

D O I：

10.1134/S1063739724700823

中图分类号：

学科分类号：

摘要：

Abstract—: With a decrease in the size of transistors, the conditions arise when the impact of one particle affects several transistors in the composition of a memory cell. Therefore, during simulation it is not sufficient to take into account one transistor directly hit by a particle. In this study, a full-size 3D model of two n-channel transistors that are part of a 6T memory cell in which the charged particle enters is considered. A particle impact simulation procedure is proposed that makes it possible to calculate the current pulse after the impact in a TCAD simulator and the response of memory cell circuit to an impact in a SPICE simulator using SPICE models. This procedure allows combining the advantages of the TCAD and SPICE calculations and achieve consistency between accuracy and the speed of simulation. The issues of determining the parameters of the TCAD model of a particle impact, the occurrence of a current pulse after a particle impact near a transistor in the on state, and the influence of the current of this transistor on the operation of a memory cell are considered. A technique of specifying the complex distribution profiles of charge carriers induced by particle impact in a TCAD simulator is proposed. Several cases of particle impact with different linear energy transfer (LET) values are simulated and an example of determining the critical LET value for a 6T SRAM cell with a design code of 28 nm is shown. The tailored parameters of the physical structure of the transistor make it possible to simulate the characteristics of transistors manufactured using the 28-nm CMOS technology node. © Pleiades Publishing, Ltd. 2024.

引用

页码：737 / 743

页数：6

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