A 35 nV/√Hz Analog Front-End Circuit with Adjustable Bandwidth and Gain in UMC 40 nm CMOS for Biopotential Signal Acquisition

This paper presents a 35 nV/root Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 M Omega at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 mu Vrms over the 0.5-1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 x 0.47 mm2 on the chip, with a power consumption of 8.96 mu W.