A 4H-SiC JFET with a monolithically integrated temperature sensor

被引：0

作者：

Monaghan F. ^{[1
]}

Martinez A. ^{[1
]}

Evans J. ^{[1
]}

Fisher C. ^{[1
]}

Jennings M. ^{[1
]}

机构：

[1] Centre of Integrative Semiconductor Materials, Swansea University

来源：

Power Electron. Devices Compon. |

基金：

英国工程与自然科学研究理事会;

关键词：

Integrated temperature sensor; JFET; P-type SiC; Silicon carbide;

D O I：

10.1016/j.pedc.2024.100069

中图分类号：

学科分类号：

摘要：

In this paper, we present a monolithically integrated temperature sensor for a 4H-SiC JFET. This uses a lateral resistor formed by the P+ gate implant. The sensor resistance is dependent on the number of ionized dopants, which increases with temperature. Drift-diffusion simulations considering device self-heating have been carried out, which show the JFET exhibits a breakdown voltage of 1480 V and a nominal threshold voltage (Vth) of −4.3 V. We show that the sensor has a high degree of linearity (R2) of 0.996 between 25–150∘C. Breakdown voltage of the JFET with the integrated sensor is found to reduce as the spacing (S) between the gate junction, the adjacent floating guard ring (FGR) and the sensor junction increases. However, it is found that a large variation in sensor current (ΔIsens) is experienced in the off-state if S is small. An optimum value of S = 0.95 µm was found to maintain 90% of the JFET breakdown voltage, whilst only exhibiting ΔIsens= 3.4%. The impact of contact resistance to the total sensor resistance is ≤1%. In addition, the sensor robustness during switch-off is good, due to the high doping in the P+ layer. The proposed sensor can be integrated into 4H-SiC JFET without any modification of existing process flows, or additional mask layers to provide real-time temperature monitoring with high accuracy. © 2024 The Author(s)

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