共 50 条
- [1] Electrical Characterization of 3D Through-Silicon-Vias 2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1100 - 1105
- [2] Electrical Modeling and Analysis of Sidewall Roughness of Through Silicon Vias in 3D Integration 2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2014, : 52 - 56
- [3] Stress Analysis in 3D IC having Thermal Through Silicon Vias (TTSV) 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2337 - 2341
- [4] Analysis of Through Silicon Vias and substrate coupling in 3D CMOS circuits by Spice simulations 2021 7TH INTERNATIONAL CONFERENCE ON ENGINEERING AND EMERGING TECHNOLOGIES (ICEET 2021), 2021, : 867 - 872
- [5] Electrical-Thermal-Structural Coupling Simulation for Electrosurgery Simulators 2011 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2011, : 322 - 325
- [6] THERMAL STRESS OF THROUGH SILICON VIAS AND SI CHIPS IN 3D SIP PROCEEDINGS OF THE ASME PACIFIC RIM TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC SYSTEMS, MEMS AND NEMS 2011, VOL 1, 2012, : 325 - +
- [7] Reliable Through Silicon Vias for 3D Silicon Applications PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 63 - +
- [8] A Wet Process To Etch Arrayed Vias For Through Silicon Via Application Of 3D Packaging 2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 1373 - 1376
- [9] Precision depth measurement of through silicon vias (TSVs) on 3D semiconductor packaging process OPTICS EXPRESS, 2012, 20 (05): : 5011 - 5016
- [10] Through Silicon Vias as Enablers for 3D Systems DTIP 2008: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS, 2008, : 119 - +