FastRMT: A High-Speed Data Plane Programmable System for Micro-Architecture Innovation

被引：0
|
作者：
Yang X.-R. [1 ]
Zeng L.-B. [1 ]
Liu Z.-P. [1 ]
Chen Y.-W. [1 ]
Lv G.-F. [1 ]
Yang C. [2 ]
Su J.-S. [1 ]
机构：
[1] School of Computer Science, National University of Defense Technology, Changsha
[2] Hunan Institute of Advanced Technology, Changsha
来源：
Jisuanji Xuebao/Chinese Journal of Computers | 2024年 / 47卷 / 02期
基金：
中国国家自然科学基金;
关键词：
data plane programmability; micro-architecture; FPGA Prototype; Programming Protocol-Independent Packet Processers(P4); Reconfigurable Match Table (RMT);
D O I：
10.11897/SP.J.1016.2024.00473
中图分类号：
学科分类号：
摘要：
Network data plane programmability(Data Plane Programmability)gives powerful programmability to the data plane of network forwarding devices, allowing the deployment of new network protocols, updating security functions, and providing in-network computing acceleration services without updating devices. Due to these advantages, data plane programmability has become an emerging technology that is highly concerned by the industry and academia, and has been put into use by mainstream cloud service providers. Among them, Reconfigurable Match Table architecture(RMT)has become a hot research direction in the programmable data plane due to its excellent processing performance and flexible programming capability with P4 language. However, due to the complex design of the RMT architecture, the closed-source service mechanism of the chip, and the high development threshold of FPGA, it is currently difficult for researchers to innovatively design the micro-architecture of the RMT architecture through FPGA and perform in real performance scenarios(above 100 Gbps). Motivated by the need of research on data plane programmable micro-architecture, this paper proposes an open-source design of a flexible and high-speed programmable data plane prototype system for the first time. The system supports core functions such as RMT architecture programmable protocol parsing, custom rule matching, and action engines based on very-long instruction words, and supports programming of the system via P4 language. In addition, FastRMT also has the characteristics of loose coupling and modularity, which facilitates researchers to replace or reconstruct modules, thereby enabling agile development and verification of new mechanisms or architectures. This work includes two versions of switch prototype and network interface card prototype, supporting mainstream FPGA chips. The system can complete 100 Gbps line-speed packet processing capability, and the 1500 B packet processing delay is only 1.22 μs, which reflects the micro-architecture innovation of FastRMT as a basic framework. and the advantages and feasibility of production line-level verification. © 2024 Science Press. All rights reserved.
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页码：473 / 490
页数：17
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