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- [6] Analytical Modeling of Potential Profile and Threshold Voltage for Rectangular Gate-all-around III-V Nanowire MOSFETs with ATLAS Verification 2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC), 2012,
- [7] Simulation and comparative study on analog/RF and linearity performance of III-V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2019, 25 (05): : 1855 - 1861