Utilizing a Novel Universal Quantum Gate in the Design of Fault-Tolerant Architecture

被引：0

作者：

Misra, Neeraj Kumar ^{[1
]}

Bhoi, Bandan Kumar ^{[2
]}

Kassa, Sankit Ramkrishna ^{[3
]}

机构：

[1] School of Electronics Engineering, VIT-AP University, Andhra Pradesh, Amaravathi,522237, India

[2] Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology, Burla, Odisha, Sambalpur,768018, India

[3] Department of Electronics and Telecommunication Engineering, Symbiosis Institute of Technology, Symbiosis International Deemed University, Pune

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摘要：

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引用

共 4 条

[1] Design and realization of the fast, flexible and fault-tolerant polyprocessor „Heidelberg POLYP
Männer, R.
Saaler, W.
Sauer, T.
von Walter, P.
Deluigi, B.
1600, De Gruyter Oldenbourg (24): : 1 - 6
[2] 64K RAM - FAULT-TOLERANT SEMICONDUCTOR MEMORY DESIGN
HUBER, WR
BELL LABORATORIES RECORD, 1979, 57 (07): : 199 - 204
[3] On the design and analysis of fault tolerant NoC architecture using spare routers
Information and Communications Research Lab., Industrial Technology Research Institute, Hsinchu, Taiwan
不详
Proc Asia South Pac Des Autom Conf, (431-436):
[4] A novel direct field-oriented control strategy for fault-tolerant control of induction machine drives based on EKF
Tabasian, Rahemeh
Ghanbari, Mahmood
Esmaeli, Abdolreza
Jannati, Mohammad
IET ELECTRIC POWER APPLICATIONS, 2021, 15 (08) : 979 - 997